The present invention relates generally to information processing systems and more particularly to a methodology and implementation for signal transmission in digital electronic systems.
Subject matter disclosed and not claimed herein is disclosed and claimed in one or more of the following related copending applications, which are assigned to the assignee of the present application and included herein by reference:
Ser. No. 09/640,544;
Ser. No. 09/640,539; and
Ser. No. 09/640,512.
In digital computer assemblies, including integrated circuit packaging, printed circuit cards or boards, and system backplanes, it has become common practice over the years to sandwich a logic signal (SIG) transmission line between two reference planes, i.e. between a power (VDD) reference plane and a power return ground (GND) reference plane, while transmitting the logic signal from a driver circuit to one or more receiver circuits. That practice alone would create a very undesirable VDD-to-GND AC switching energy storage and transmission system problem between the two reference planes. In order to minimize that problem, many de-coupling capacitors have been coupled between the two planes. The de-coupling capacitors are effective to AC-short-circuit the two reference planes together. Such de-coupling capacitors are connected to each plane by vias to form a three part series combination of via-component-via. Thus there is formed a signal transmission system which also doubles as a DC power (VDD) and DC power ground (GND) return since the reference planes are DC-isolated but AC-short-circuited. In this manner power, power, return and logic signals may be efficiently packaged with the fewest number of conducting layers. However, switching energy and reference potential noise continue to be a problem especially as system switching frequencies continue to increase.
Thus there is a need for an improved methodology and implementing system which provides for improved signal transmission in a digital signal processing system while blocking switching energy and reference potential noise from entering the system reference potential distribution architecture.
A method and implementing computer system are provided in which continuous reference potential planes are connected together by direct short-circuit connections. In an exemplary embodiment, de-coupling capacitors are eliminated and short-circuit connections are provided through the use of vias connecting reference potential planes together and transmitting logic signals from a driver to one or more receivers between two potential reference planes. In one exemplary embodiment, power (VDD) planes are connected together with vias through a circuit board construction and in a second exemplary embodiment ground (GND) planes are similarly connected together.